The present invention generally relates to digital communications, and more particularly to a delay lock loop (DLL) circuit for improving setup and hold times for a parallel data communication system.
Digital communications promises faster, flexible, and more reliable speeds than conventional analog communications. Accordingly, various time measurements become critical. For instance, in a digital communication system, setup time represents the length of time that a pulse is held in order to produce a state change. Hold time represents the length of time a signal is maintained at a certain input after changing state at another input. Low setup and hold times are important, especially for high speed parallel data.
The setup and hold time windows on high speed data lines can be degraded by clock driver and data driver skew, duty cycle distortion of data drivers, clock and data jitter, and power supply noise. High speed data from different physical locations on a chip suffers not only from poor setup and hold times, but also clock skew in passing clock information to the various different physical locations. Some clock distribution schemes exist for providing synchronized clock signals to different locations, however there is a need for a clock distribution network that also improves setup and hold times for physically separated parallel data.